1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip design, and more particularly, to modeling spatial correlations of circuit design device parameters.
2. Background Art
As integrated circuit (IC) chip processing technology continues miniaturization from 65 nanometer (nm) to 45 nm to 32 nm node technologies, the variations in the semiconductor processing become larger and larger, and need for a proper analysis in device modeling and circuit simulations increases. In semiconductor processing and devices as well as in logic circuits the intra-die variations and/or inter-die variations exhibit spatial correlations. Namely, measured hardware data has shown that spatial correlations exist between two device instances (e.g., logic circuits, devices, or the electric parameters of two devices) located within a chip/die or located on different dies/chips in the same wafer. In addition, data shows that the degree of the spatial correlation generally decreases with increasing separation between the devices.
Most conventional approaches to modeling spatial correlations use a principal component analysis (PCA). However, the PCA approaches do not address how to handle the problem when one or more negative eigenvalues arise. The situation of negative eigenvalues often arises due to poorly filled in correlation coefficients. Also, the PCA approaches do not give an insight on how to extend the result to the limit of very small grid size. When the PCA approaches are used for a large number of sub-regions (i.e., for a very small grid size), it often results in many terms for each instance of a device parameter and thus leads to a much longer circuit simulation time.